The present invention relates to semiconductor packages, and more particularly, to a semiconductor package in which a chip carrier having a plurality of downwardly extending portions is used, in place of a die pad, to accommodate a semiconductor chip thereon.
In response to a trend in profile miniaturization of electronic products, semiconductor devices are desirably made with reduction of costs, high performance and compactness in size. Accordingly, several small-scale semiconductor packages are developed, for example, a TSOP (thin small outline package), SSOP (shrink small outline package) or TQFP (thin quad flat package) is dimensioned in thickness of only 1 mm, and even a UTSOP (ultra thin small outline package) is merely 0.75 mm thick. Further, a semiconductor package is preferably incorporated with two or more semiconductor chips, so as to enhance its integrated circuit density, memory capacity and processing speed.
U.S. Pat. No. 5,527,740 discloses a multi-chip thin semiconductor package. As shown in FIG. 1, this conventional semiconductor package 1 employs a lead frame 10, in which an adhesive layer 11 is formed on each of front and back sides 100, 101 of a die pad 102 of the lead frame 10, allowing a first chip 12 and a second chip 13 to be mounted on the back and front sides 101, 100 of the die pad 102, respectively. A plurality of first gold wires 14 and second gold wires 15 are used to electrically connect the first and second chips 12, 13 to leads 103 positioned around the die pad 102. And an encapsulant 16 is formed to encapsulate the first chip 12, the second chip 13, the gold wires 14, 15 and partially the leads 103, so as to prevent chip surfaces from being damaged by external moisture and contaminant.
In such a conventional lead-frame based semiconductor package, the die pad 102 is designed correspondingly to predetermined chip dimensions. As shown in FIG. 2, during a molding process, a melted molding resin 16 (designated by the same numeral as the encapsulant 16) is injected into an encapsulating mold 19. A mold flow of the molding resin 16 is impeded when flowing to the die pad 102 and the first and second chips 12, 13 mounted on the die pad 102, and diverted into an upper mold flow 17 and a lower mold flow 18, wherein the upper mold flow 17 passes the second gold wires 15, the second chip 13 and an upper mold cavity 192 of the encapsulating mold 19, while the lower mold flow 18 goes through the first gold wires 14, the first chip 12 and a lower mold cavity 193 of the encapsulating mold 19; this then entirely encapsulates the die pad 102 and the first and second chips 12, 13 in the encapsulant 16. However, in response to miniaturization in package profile (i.e. reduction in mold cavity height of the encapsulating mold 19), the foregoing semiconductor package 1 generates several problems. First, the encapsulant 16 of the semiconductor package 1 decreases in thickness due to height reduction of mold cavities 192, 193; this deteriorates mechanical strength of the encapsulant 16, and possibly results in delamination occurring at interfaces among the chips 12, 13, the die pad 102 and the encapsulant 16 formed on the chips 12, 13 due to differences in coefficients of thermal expansion during a temperature cycle in subsequent fabrication processes, so that quality and reliability of fabricated products are seriously degraded.
On the other hand, when overall height H of the mold cavities 192, 193 is reduced to 1 mm or even to 0.75 mm (as used for the above UTSOP semiconductor package), after combined thickness including the first and second chips 12, 13, the adhesive layers 11, 11 formed on the front and back sides 100, 101 of the die pad 102 and the die pad 102 itself, is subtracted from the overall height H, it can be calculated from the below equation that a gap left in each of the mold cavities 192, 193 is only 8 mils wide in average (one mil equals to one thousandth of an inch) for allowing the upper mold flow 17 or the lower mold flow 18 to pass therethrough. The equation is illustrated as follows:
[1xe2x88x92(0.2xc3x972+0.03xc3x972+0.13)]/2=0.205(mm) (this is approximately equal to 8 mils),
wherein the overall height H of the mold cavities is 1 mm, a single chip is 0.2 mm thick, a single adhesive layer is 0.03 mm thick, and the die pad is 0.13 mm in thickness.
As only the 8-mil gap is left between a top surface of the mold cavity and the chip for allowing the mold flow to go therethrough, such a gap is actually the minimal space permeable for the mold flow, and thus it often results in voids in encapsulant 16 due to incomplete filling with the molding resin or air left in the mold cavity. In FIG. 2 in case of the gold wires 14, 15 having wire loop height of 6 mils, then a gap xe2x80x9csxe2x80x9d between wire loops and the mold cavity for allowing the mold flow to go therethrough can only be 2 mils wide. Such a gap is so narrow and difficult to be permeated by the mold flow, and unbalanced speed of upper and lower mold flows 17, 18 easily result in die pad floating, thereby making the first gold wires 14 exposed to the outside of the encapsulant 16, as indicated by the dotted-line circle in FIG. 2.
In addition, U.S. Pat. No. 5,793,108 discloses another multi-chip thin semiconductor package with stacked chips mounted on a front side of a die pad. As shown in FIG. 3, this semiconductor package 1xe2x80x2 is fabricated in a manner that, a first chip 12xe2x80x2 is attached onto a die pad 102xe2x80x2 with its front surface (circuit surface) facing downwardly, and then a second chip 13xe2x80x2 is stacked on a back surface of the first chip 12xe2x80x2. The first and second chips 12xe2x80x2, 13xe2x80x2 are both dimensionally larger than the die pad 102xe2x80x2, so as to reduce contact area between the chip 12xe2x80x2 and the die pad 102xe2x80x2. Subsequently, after the chips 12xe2x80x2, 13xe2x80x2 are electrically connected to a plurality of leads 103xe2x80x2 positioned around the die pad 102xe2x80x2 by means of gold wires 14xe2x80x2, 15xe2x80x2, an encapsulant 16xe2x80x2 is formed to encapsulate the first chip 12xe2x80x2, the second chip 13xe2x80x2, the gold wires 14xe2x80x2, 15xe2x80x2, and the die pad 102xe2x80x2; this then completely fabricates the multi-chip semiconductor package 1xe2x80x2.
However, such a semiconductor package 1xe2x80x2 also has similar problems or drawbacks as the above semiconductor package 1 disclosed in U.S. Pat. No. 5,527,740. Referring to FIG. 4, in order to provide more space for accommodating chips without altering the package profile, the semiconductor package 1xe2x80x2 has the die pad 102xe2x80x2 positioned lower in elevation than a plane formed by the leads 103xe2x80x2. Such an arrangement however significantly narrows down a gap between the die pad 102xe2x80x2 and a lower mold cavity 193xe2x80x2 for allowing a mold flow to pass therethrough, and thereby makes a lower mold flow 18xe2x80x2 that goes through the narrowed gap move much slower than an upper mold flow 17xe2x80x2. Then, the upper mold flow 17xe2x80x2 rapidly encapsulates the chip 13xe2x80x2, and generates a downward pressure that presses the die pad 102xe2x80x2; this results in die pad floating and undesirably makes the gold wires 14xe2x80x2, 15xe2x80x2 exposed to the outside of the encapsulant 16xe2x80x2.
A primary objective of the present invention is to provide a multi-chip thin semiconductor package, in which a chip carrier with a plurality of downwardly extending portions is used, in place of a die pad, for accommodating semiconductor chips thereon, so as to balance upper and lower mold flows, and prevent die pad floating from occurrence.
Another objective of the invention is to provide a multi-chip thin semiconductor package with a chip carrier having a plurality of downwardly extending portions, so as to balance upper and lower mold flows, and prevent gold wires from being exposed to the outside of an encapsulant.
Still another objective of the invention is to provide a multi-chip thin semiconductor package with a chip carrier having a plurality of downwardly extending portions, so as to reduce the occurrence of delamination among the chips, the die pad and the encapsulant that is caused by different thermal stresses applied on the chip carrier and the chips.
A further objective of the invention is to provide a multi-chip thin semiconductor package with a chip carrier having a plurality of downwardly extending portions, in place of a die pad, so that space previously occupied by the die pad is used for allowing a mold flow to pass therethrough with reduced flow resistance, so as to improve fluidity of a mold flow, and avoid the formation of voids in an encapsulant of the semiconductor package.
A further objective of the invention is to provide a multi-chip thin semiconductor package with a chip carrier with a plurality of downwardly extending portions, in place of a die pad, so that more space is provided for accommodating more semiconductor chips.
In accordance with the above and other objectives, the present invention proposes a multi-chip thin semiconductor package, comprising: a lead frame having at least one chip carrier formed at a central position thereof and a plurality of leads surrounding the chip carrier, wherein the chip carrier is dimensionally smaller in surface area and width than chips to be mounted on the chip carrier, and consists of at least one supporting frame and a plurality of downwardly extending portions integrally formed with the supporting frame; a first chip having its front surface attached onto a surface of the supporting frame by means of an adhesive layer, and electrically connected to the leads by a plurality of first gold wires; a second chip stacked on a back surface of the first chip and electrically connected to the leads by a plurality of second gold wires; and an encapsulant formed by a molding compound for encapsulating the semiconductor chips, the gold wires and partially the leads.
As compared to a conventional semiconductor package in the use of a die pad, the invention employs the chip carrier with the downwardly extending portions formed on the lead frame, in place of the die pad, for accommodating the semiconductor chips thereon. Since the extending portions integrally connected with the supporting frame only occupy small space, this therefore relatively reduces contact area between the supporting frame and the first chip, so that delamination can be prevented from occurrence that is caused by different thermal stresses applied to the supporting frame and the first chip. Further, the provision of the chip carrier does not impede a mold flow of the molding compound, but provides more space for the mold flow to pass therethrough, wherein the enlarged space in each side of a mold cavity is around 11.2 mils wide that is calculated by subtracting heights of two semiconductor chips (0.2 mmxc3x972) and an adhesive layer (0.03 mm) from entire height of the mold cavity (1 mm), i.e. [1xe2x88x920.2xc3x972xe2x88x920.03]/2=0.285 mm=11.2 mils. Such a space is significantly larger than a gap of 8 mils wide as previously calculated for the conventional semiconductor package. As a result, the enlarged space provided for the mold flow can accordingly improve the fluidity of the mold flow, and eliminates problems of incomplete filling with the molding compound and formation of voids. Moreover, since the chip carrier does not interfere with the mold flow, thus the downwardly extending portions can be dimensioned as to even reduce the space between the first chip and a lower mold cavity to a minimal gap of 8 mils wide, so as to maximally maintain space above the second chip for accommodating more chips.
On the other hand, the downwardly extending portions of the chip carrier can function as a pre-stressed structure, which can generate a pre-stressing force for allowing the extending portions to closely abut the bottom of the lower mold cavity after mold engagement; this can therefore prevent the chip carrier from being dislocated due to mold flow impact, and eliminate partial exposure of the gold wires to the outside of the encapsulant.